1. Field of the Invention
The present invention relates to a reference-voltage generating circuit that supplies a constant reference voltage to electronic equipment components mounted on portable equipment susceptible to temperature changes or power supply voltage fluctuations.
2. Description of the Related Art
The electronic equipment components mounted on portable equipment such as a portable telephone or notebook-type personal computer are by nature largely susceptible to temperature changes or power voltage fluctuations. The portable telephone, for example, is required to be assured of normal operation against temperature changes of -30.degree. C. to +90.degree. C. Moreover, such portable equipment, which employs rechargeable batteries as its power supply, is required to operate in a stable manner against a certain extent of power voltage fluctuations.
To improve the accuracy and the performance of electronic equipment components mounted on such portable equipment against temperature changes and power voltage fluctuations, it is necessary to regulate voltage with which the internal circuits of those components are driven, and against temperature changes or power voltage fluctuations.
For this purpose, a constant-voltage generating circuit (regulator circuit) which regulates the drive voltage needs to have a reference-voltage generating circuit which generates a reference voltage to keep the regulation output potential at a constant level.
That is, for the internal circuits of an electronic equipment component to operate in a stable manner against temperature changes or power voltage fluctuations, it is necessary to provide an invariable value of voltage which is supplied by the constant-voltage generating circuit in order to drive those internal circuits.
The constant-voltage generating circuit in general is used in combination with a reference-voltage generating circuit, which supplies a reference potential for the potential regulation. An example of such combination of reference-voltage generating circuit and constant-voltage generating circuit is disclosed in Japanese Patent Laid-Open Publication No. 3-180915.
Generally, the internal circuits of electronic-equipment components are made up of semiconductor ICs and, more specifically, those reference-voltage generating circuits and constant-voltage generating circuits are composed of analog circuits which are made up of discrete MOS transistors. In these circuits, the voltage at which a discrete MOS transistor changes from the ON state to the OFF state is called the threshold voltage of that transistor and stays the same even for the opposite transition of state (i.e. change from the OFF state to the ON state). The current threshold voltage for typical MOS transistors used in logic circuits is approximately 0.7V.
FIG. 5 shows a circuit diagram of a prior-art reference-voltage generating circuit as disclosed in Laid-Open Publication 3-180915.
First, the following describes the configuration of a prior-art reference-voltage generating circuit with reference to FIG. 5.
In this reference-voltage generating circuit, the sources of all of three p-channel MOS transistors MP1, MP2, and MP3 are connected to a higher-potential power supply VDD. Note here that in FIG. 5, the gate, the source, and the drain of the MOS transistors are represented by G, S, and D respectively.
The gate of the p-channel MOS transistor MP1 is connected to the gate and the drain of the p-channel MOS transistor MP2; the drain of the p-channel MOS transistor MP1 is connected to the drain of an n-channel MOS transistor MN1; and the drain of the p-channel MOS transistor MP2 is connected to the drain of an n-channel MOS transistor MN2.
Moreover, the sources of both the n-channel MOS transistors MN1 and MN2 are connected to ground (earth) GND through a first constant-current circuit IC1.
Further, the p-channel MOS transistors MP1 and MP2, the n-channel MOS transistors MN1 and MN2, and the first constant-current circuit IC1 make up a differential amplifier OPA.
The drain of the n-channel MOS transistor MN1 is connected to both the gate of the p-channel MOS transistor MP3 and one terminal of a phase-compensation capacitor PC1. The drain of p-channel MOS transistor MP3 is in turn connected to the other terminal of the phase-compensation capacitor PC1 and also to GND through a second constant-current circuit IC2.
With this, the p-channel MOS transistor MP3, the phase-compensation capacitor PC1, and the second constant-current circuit IC2 constitute an output circuit OC1, providing its output terminal OUT at the drain of the p-channel MOS transistor MP3.
Further, between the output terminal OUT and GND, three resistors R1, R2, and R3 are connected in series; the gate of the n-channel MOS transistor MN1 is connected to the connection between resistors R2 and R3; and the gate of the n-channel MOS transistor MN2 is connected to the connection between resistors R1 and R2, thus making up a reference-voltage generating circuit.
The following explains how this prior-art reference-voltage generating circuit operates.
The serial circuit made up of the resistors R1, R2, and R3 provides a feedback to the gates of both the first and the second n-channel MOS transistors MN1 and MN2.
With this, the serial circuit of the resistors R1, R2, and R3 amplifies an offset voltage, which is a difference (VGS2-VGS1) between VGS1, i.e. the gate-source voltage of the n-channel MOS transistor MN1 and VGS2, i.e. the gate-source voltage of the n-channel MOS transistor MN2.
Therefore, the output voltage VOUT appearing at the output terminal OUT is as follows: EQU VOUT=(VGS2-VGS1 ).times.(R1+R2+R3)/R2 (1)
Representing here the threshold voltages of the n-channel MOS transistors MN1 and MN2 and the drain currents flowing through them by VTH1, VTH2, I1, and I2, respectively, the following equations (2) and (3) are obtained based on the saturation equation for MOS transistors: EQU I1=K1.times.(VGS1-VTH1)2 (2) EQU I2=K2.times.(VGS2-VTH2)2 (3)
where K1 and K2 are conductivity coefficients.
If, here, the conductivity coefficients K1 and K2 of n-channel MOS transistors MN1 and MN2 as well as the conductivity coefficients and also the threshold voltages of the p-channel MOS transistors are designed to be equal to each other, respectively, k1=k2 and I1=I2 are obtained, thereby giving the following equation based on the above-mentioned equations (2) and (3): EQU VGS2-VGS1=VTH2-VTH1 (4)
where VGS2-VGS1 is an offset voltage, which is equal to VTH2-VTH1, i.e. a difference in threshold voltage between the n-channel MOS transistors MN1 and MN2. The temperature characteristics of the threshold level of the same conductivity type of MOS transistors are almost the same, so that a reference voltage VREF of good temperature characteristic can be obtained as indicated by the following equation (5): EQU VREF=VTH2-VTH1 (5)
Therefore, by substituting Equations (4) and (5) into Equation (1), it is possible to obtain an output voltage VOUT given in the following equation (6) having good temperature characteristics and being independent of power-supply voltage fluctuations: EQU VOUT=VREF.times.(R1+R2+R3)/R2 (6)
The resistors R1 and R2 in this case may well be 0.OMEGA. in value.
Also, the offset voltage may be output by employing n-channel MOS transistors MN1 and MN2 that have mutually different threshold voltages; by employing such p-channel MOS transistors MP1 and MP2 that have mutually different threshold voltages; or by constituting the MOS transistors in such a way as to be of the same conductivity type, but of different sizes.
The first constant-current circuit IC1 here keeps at a constant level a current following through the differential amplifier OPA, which current is divided into two equals by a so-called "current mirror circuit" constituted by the two p-channel MOS transistors MP1 and MP2.
With this, independently of power-supply voltage fluctuations or temperature changes, the same magnitude of drain-source current will flow through both p-channel MOS transistors MP1 and MP2.
Again, the gate of the p-channel MOS transistor MP1 is connected to the gate and the drain of the p-channel MOS transistor MP2.
Therefore, the same value of gate-source voltage is applied to both p-channel MOS transistors MP1 and MP2.
As can be seen from the VDS (drain-source voltage) vs. IDS (drain-source current) relationship, therefore, the operational amplifier OPA is stable when the drain-source voltage is equal for the p-channel MOS transistors MP1 and MP2 and, at the same time, the drain-source voltage is equal for the n-channel MOS transistors MN1 and MN2.
The VDS vs. ISD characteristics curve for n-channel MOS transistors is shown in FIG. 6.
In FIG. 6, the horizontal axis represents VDS (drain-source voltage) and the vertical axis, IDS (drain-source current). The same value of current flowing through both p-channel MOS transistors MP1 and MP2 is indicated by the dash-and-dot line IDP.
Again, the reference-voltage generating circuit shown in FIG. 5 has three resistors R1, R2, and R3 connected in series between the ground GND and the output terminal OUT of the output circuit.
With this configuration, the gate-source voltage of the n-channel MOS transistor MN1 is always closer in value to the GND potential than that of the n-channel MOS transistor MN2.
In this case, in FIG. 6 showing the VDS vs. IDS characteristics curve, the gate-source voltage of the n-channel MOS transistor MN1 is expressed by the curve VG1 and that of the n-channel MOS transistor MN2, by the curve VG2. The intersection of curve VG1 and dash-and-dot line IDP showing the same current flowing both the p-channel MOS transistors MP1 and MP2 indicates a drain-source voltage VD1 of the n-channel MOS transistor MN1, while the intersection of dash-and-dot line IDP and VG2 indicates a drain-source voltage VD2 of the n-channel MOS transistor MN2.
With this, for the differential amplifier OPA to be stable in operation, it is necessary that the drain-source voltage VD1 of the n-channel MOS transistor MN1 and the drain-source voltage VD2 of the n-channel MOS transistor MN2 be equal to each other.
Also, since the drain-source voltage VD1 of the n-channel MOS transistor MN1 is applied to the gate of the p-channel MOS transistor MP3, the drain-source voltage VD1 of the n-channel MOS transistor MN1 is higher in valve than the drain-source voltage VD2 of the n-channel MOS transistor MN2 and, at the same time, the drain potential of the p-channel MOS transistor MP3 gets closer in value to the GND potential.
However, the reference-voltage generating circuit shown in FIG. 5 has resistors R1, R2, and R3 connected in series between the GND terminal and the output terminal OUT of the output circuit OC1, so that some difference in potential always appears between the gate of the n-channel MOS transistor MN1 and that of the other n-channel MOS transistor MN2. Therefore, the differential amplifier OPA is stable only when the gate potential of the n-channel MOS transistor MN1 and that of the n-channel MOS transistor MN2 are both equal to the GND potential.
That is, the differential amplifier is stable only when the output voltage VOUT appearing at the output terminal OUT is equal to the potential of the GND terminal.
This means that based on the operation principle of the comparator circuit utilizing the configuration of the differential amplifier OPA, when mutually different potentials are applied at the two input terminals of the differential amplifier OPA, this amplifier outputs the potential of either the higher level power supply voltage or the lower level power supply voltage.
Also, even with such a reference-voltage generating circuit configuration as shown in FIG. 5, a desired level of output voltage VOUT will appear at the output terminal OUT when the p-channel MOS transistors MP1 and MP2 constituting a current-mirror circuit have mutually different threshold voltages or transistor dimensions or when, likewise, the n-channel MOS transistors MN1 and MN2 do so.
However, if the n-channel MOS transistors MN1 and MN2 have mutually different threshold voltages or if the p-channel MOS transistors MP1 and MP2 of the same conductivity type likewise do so, or have mutually different transistor dimensions, the temperature characteristics of these MOS transistors change.
The temperature characteristics of transistors change in general with, for example, the threshold voltage and the current density of drain-source currents flowing though channel regions, so that a plurality of transistors with mutually different threshold voltages have mutually different temperature characteristics.
Also, when transistors having different dimensions are employed, those transistors have mutually different current densities of the drain-source current flowing through their channel regions, with the current flowing through the differential amplifier OPA being constant due to the constant-current circuit IC1, so that those transistors have mutually different temperature characteristics.
With this, therefore, such transistors that have mutually different threshold voltages or transistor dimensions are employed to give rise to an offset voltage, thus enabling a desired level of output voltage VOUT which is stable against power supply voltage fluctuations even with the configuration of reference-voltage generating circuit shown in FIG. 5. In this case, however, this arrangement will be worsened in stability against temperature changes.
This is because if the p-channel MOS transistors MP1 and MP2 have mutually different threshold voltages or transistor dimensions, the drain-source current changes in a different manner between these two MOS transistors, so that it is impossible to keep the output voltage at a constant level.
Also, if the n-channel MOS transistors MN1 and MN2 have mutually different threshold voltages or transistor dimensions, those two MOS transistors have mutually different temperature characteristics, so that it is impossible to keep the output voltage VOUT constant.
In addition, if two transistors have mutually different transistor dimensions or threshold voltages, variations through the fabrication process have different influences on those transistors, bringing about large variations in the value of the output voltage VOUT.